- questions
    - interrupt:
        - flush instructions in-flight? (exceptions!)
        - allow in-flight instr. to complete? (exceptions!)
            - priorities exc. vs int.
        - context switches:
            - save entire context (= all regs) to stack?
            - execution of interrupt procedure
        - multiple exceptions simultaneously? => prioritization
            - only handle newest exceptions, flush pipeline? set pc to last uncommitted instruction?
        - for mispred.: latch correct pc as return address!
        - exc./int. part of ctrl?
        - CSR unit into ctrl (and arbitrate, requests from exec?)
        - refator to keep changes to be made by students minimal?
        - CSR unit with int vector/exc vector in registered operation
            - exception priorities (let higher priorities pre-empt lower priorities?
                - in official spec! (illegal instr. > misaligned load/store)
            - MiRiV load/store exceptions: misalignment?
            - how to deal with exceptions raised during wrong branches?
        - exception inside exception?
- feedback:
    - nicht verkünsteln! (sehr wichtiges feedback)
    - einfache exception/interrupt behandlung
    - zeitplan update? optional
    - CSR unit read only on csrread?
    - MiRiV pipeline image generation
